{"id":7592,"date":"2022-11-14T17:18:17","date_gmt":"2022-11-14T16:18:17","guid":{"rendered":"https:\/\/easii-ic.com\/adicsys\/"},"modified":"2022-11-16T17:16:10","modified_gmt":"2022-11-16T16:16:10","slug":"adicsys","status":"publish","type":"page","link":"https:\/\/easii-ic.com\/en\/adicsys\/","title":{"rendered":"ADICSYS"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"7592\" class=\"elementor elementor-7592 elementor-7581\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-9ceaa33 elementor-section-full_width elementor-section-height-min-height elementor-section-height-default elementor-section-items-middle\" data-id=\"9ceaa33\" data-element_type=\"section\" data-settings=\"{&quot;jet_parallax_layout_list&quot;:[],&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-1882f9d\" data-id=\"1882f9d\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap\">\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-96fbedc elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"96fbedc\" data-element_type=\"section\" data-settings=\"{&quot;jet_parallax_layout_list&quot;:[]}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-dc6eaae\" data-id=\"dc6eaae\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-0fa2615 elementor-widget elementor-widget-heading\" data-id=\"0fa2615\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.19.0 - 07-02-2024 *\/\n.elementor-heading-title{padding:0;margin:0;line-height:1}.elementor-widget-heading .elementor-heading-title[class*=elementor-size-]>a{color:inherit;font-size:inherit;line-height:inherit}.elementor-widget-heading .elementor-heading-title.elementor-size-small{font-size:15px}.elementor-widget-heading .elementor-heading-title.elementor-size-medium{font-size:19px}.elementor-widget-heading .elementor-heading-title.elementor-size-large{font-size:29px}.elementor-widget-heading .elementor-heading-title.elementor-size-xl{font-size:39px}.elementor-widget-heading .elementor-heading-title.elementor-size-xxl{font-size:59px}<\/style><h1 class=\"elementor-heading-title elementor-size-default\">ADICSYS is an EASii IC subsidiary developing  <br>and distributing customizable<br>Field Programmable Gate Array technology.<\/h1>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-ad8148a elementor-widget elementor-widget-text-editor\" data-id=\"ad8148a\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.19.0 - 07-02-2024 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#69727d;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#69727d;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p class=\"MsoNormal\" style=\"text-align: justify;\"><span lang=\"EN-US\">ADICSYS stands at the crossroads of ASIC design and FPGA. The company is built on more than <strong>ten years of experience <\/strong>in custom <strong>FPGA <\/strong>and <strong>embedded FPGA, or eFPGA,<\/strong> projects as well as leading edge semiconductor products. ADICSYS designs and licenses <strong>soft eFPGA IP (standard cell based) <\/strong>for ASICs and SOCs. These embedded FPGAs are <strong>technology independent <\/strong>and fully integrated into <strong>standard RTL design flows<\/strong><\/span><\/p>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-417ef3a elementor-widget elementor-widget-image\" data-id=\"417ef3a\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.19.0 - 07-02-2024 *\/\n.elementor-widget-image{text-align:center}.elementor-widget-image a{display:inline-block}.elementor-widget-image a img[src$=\".svg\"]{width:48px}.elementor-widget-image img{vertical-align:middle;display:inline-block}<\/style>\t\t\t\t\t\t\t\t\t\t<img fetchpriority=\"high\" decoding=\"async\" width=\"800\" height=\"195\" src=\"https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192528.png\" class=\"attachment-large size-large wp-image-7665\" alt=\"\" srcset=\"https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192528.png 892w, https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192528-300x73.png 300w, https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192528-768x187.png 768w\" sizes=\"(max-width: 800px) 100vw, 800px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-3eea793 elementor-widget elementor-widget-image\" data-id=\"3eea793\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<img decoding=\"async\" src=\"https:\/\/easii-ic.com\/wp-content\/uploads\/elementor\/thumbs\/Capture-decran-2022-11-14-192408-pxpnkfc5hyoorqp2ieya1tjhmmrs0utz66wb1pz1mo.png\" title=\"Capture d\u2019\u00e9cran 2022-11-14 192408\" alt=\"Capture d\u2019\u00e9cran 2022-11-14 192408\" loading=\"lazy\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-88f55be elementor-widget elementor-widget-image\" data-id=\"88f55be\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<img decoding=\"async\" width=\"800\" height=\"86\" src=\"https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192122.png\" class=\"attachment-large size-large wp-image-7653\" alt=\"\" srcset=\"https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192122.png 873w, https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192122-300x32.png 300w, https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192122-768x83.png 768w\" sizes=\"(max-width: 800px) 100vw, 800px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-9741983 elementor-widget elementor-widget-image\" data-id=\"9741983\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<img decoding=\"async\" src=\"https:\/\/easii-ic.com\/wp-content\/uploads\/elementor\/thumbs\/Capture-decran-2022-11-14-192135-pxpnhy1hgpag4sarzucpyy2p70zwplzh5wx6gfng1s.png\" title=\"Capture d\u2019\u00e9cran 2022-11-14 192135\" alt=\"Capture d\u2019\u00e9cran 2022-11-14 192135\" loading=\"lazy\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-e1df659 elementor-widget elementor-widget-image\" data-id=\"e1df659\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<img decoding=\"async\" width=\"800\" height=\"463\" src=\"https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192146-1024x593.png\" class=\"attachment-large size-large wp-image-7649\" alt=\"\" srcset=\"https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192146-1024x593.png 1024w, https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192146-300x174.png 300w, https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192146-768x445.png 768w, https:\/\/easii-ic.com\/wp-content\/uploads\/2022\/11\/Capture-decran-2022-11-14-192146.png 1059w\" sizes=\"(max-width: 800px) 100vw, 800px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-7328034 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"7328034\" data-element_type=\"section\" data-settings=\"{&quot;jet_parallax_layout_list&quot;:[]}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-283af7e\" data-id=\"283af7e\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-1aea528 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"1aea528\" data-element_type=\"section\" data-settings=\"{&quot;jet_parallax_layout_list&quot;:[]}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-inner-column elementor-element elementor-element-7908309\" data-id=\"7908309\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-229de3e elementor-widget elementor-widget-heading\" data-id=\"229de3e\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Key features<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-033e67f elementor-widget elementor-widget-text-editor\" data-id=\"033e67f\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul style=\"margin-top: 0cm;\" type=\"square\">\n \t<li class=\"MsoNormal\"><span lang=\"EN-GB\">Synthesizable IP<\/span><\/li>\n \t<li class=\"MsoNormal\"><span lang=\"EN-GB\">Fully integrated into standard flows<\/span><\/li>\n \t<li class=\"MsoNormal\"><span lang=\"EN-GB\">RTL to FPGA bitstream<\/span><\/li>\n \t<li class=\"MsoNormal\"><span lang=\"EN-GB\">Technology independent<\/span><\/li>\n \t<li class=\"MsoNormal\"><span lang=\"EN-GB\">Highly scalable and customizable<\/span><\/li>\n \t<li class=\"MsoNormal\"><span lang=\"EN-GB\">Bist for manufacturing test<\/span><\/li>\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-inner-column elementor-element elementor-element-69eaac1\" data-id=\"69eaac1\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-760f9ba elementor-widget elementor-widget-heading\" data-id=\"760f9ba\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Domain specific FPGA<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-029a9cc elementor-widget elementor-widget-text-editor\" data-id=\"029a9cc\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<ul style=\"margin-top: 0cm;\" type=\"square\">\n \t<li class=\"MsoNormal\"><span lang=\"EN-GB\">FPGA core based on proven eFPGA<\/span><\/li>\n \t<li class=\"MsoNormal\"><span lang=\"EN-GB\">RTL to bitstream compilation flow<\/span><\/li>\n<\/ul>\n<p class=\"MsoNormal\" style=\"margin-left: 49.65pt;\"><span lang=\"EN-GB\">\u25aa Independent and distributable<\/span><\/p>\n<p class=\"MsoNormal\" style=\"margin-left: 49.65pt;\"><span lang=\"EN-GB\">\u25aa Embeddable in final application<\/span><\/p>\n&nbsp;\n<ul style=\"margin-top: 0cm;\" type=\"square\">\n \t<li class=\"MsoNormal\"><span lang=\"EN-GB\">Specialized Team: 20 years of FPGA core design and integration<\/span><\/li>\n<\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-43e3991 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"43e3991\" data-element_type=\"section\" data-settings=\"{&quot;jet_parallax_layout_list&quot;:[]}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-ad80ccc\" data-id=\"ad80ccc\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-6abd0b1 elementor-widget elementor-widget-image\" data-id=\"6abd0b1\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<img decoding=\"async\" src=\"https:\/\/easii-ic.com\/wp-content\/uploads\/elementor\/thumbs\/Capture-decran-2022-11-14-192158-pxpnhv7yw76l5yevgb4u9gsbevdt2ioa5iyq0lrmkg.png\" title=\"Capture d\u2019\u00e9cran 2022-11-14 192158\" alt=\"Capture d\u2019\u00e9cran 2022-11-14 192158\" loading=\"lazy\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-bd6179d elementor-widget elementor-widget-text-editor\" data-id=\"bd6179d\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"MsoNormal\" style=\"line-height: normal;\"><b><span lang=\"EN-US\">Programmable IPs in our catalog:<\/span><\/b><\/p>\n<p class=\"MsoListParagraph\" style=\"margin-bottom: 0cm; text-indent: -18pt; line-height: normal; padding-left: 40px;\">\u00a7 Immediate access &#8211; Download efpga IP datasheet<\/p>\n<p class=\"MsoNormal\" style=\"margin-bottom: 0cm; line-height: normal;\"><b><span lang=\"EN-US\"><\/p>\n<p><\/span><\/b><\/p>\n<p class=\"MsoNormal\" style=\"line-height: 150%;\"><b><span lang=\"EN-US\">Customized programmable IPs:<\/span><\/b><\/p>\n<p class=\"MsoListParagraphCxSpFirst\" style=\"text-indent: -18pt; line-height: 150%; padding-left: 40px;\">\u00a7 Dimensions and aspect ratio<\/p>\n<p class=\"MsoListParagraphCxSpMiddle\" style=\"text-indent: -18pt; line-height: 150%; padding-left: 40px;\">\u00a7 Architecture parameters (LUT count and style, routing density&#8230;)<\/p>\n<p class=\"MsoListParagraphCxSpMiddle\" style=\"text-indent: -18pt; line-height: 150%; padding-left: 40px;\">\u00a7 Customization for special constraints (area, performance, power)<\/p>\n<p class=\"MsoListParagraphCxSpLast\" style=\"text-indent: -18pt; line-height: 150%; padding-left: 40px;\">\u00a7 Customization for special design types or use case<\/p>\n<p class=\"MsoNormal\" style=\"line-height: 150%;\"><b><span lang=\"EN-US\"><br \/>Verilog programmable IP comprising:<\/span><\/b><\/p>\n<p class=\"MsoListParagraphCxSpFirst\" style=\"text-indent: -18pt; line-height: 150%; padding-left: 40px;\">\u00a7 Synthesizable RTL &#8211; Constraint files<\/p>\n<p class=\"MsoListParagraphCxSpMiddle\" style=\"text-indent: -18pt; line-height: 150%; padding-left: 40px;\">\u00a7 ADICSYS compilation software: Acompile<\/p>\n<p class=\"MsoListParagraphCxSpLast\" style=\"text-indent: -18pt; line-height: 150%; padding-left: 40px;\">\u00a7 Bitstream loader &amp; Test program (BIST)<\/p>\n<p class=\"MsoNormal\" style=\"margin-bottom: 0cm; line-height: normal;\"><b><span lang=\"EN-US\"> <\/span><\/b><\/p>\n<p class=\"MsoNormal\" style=\"margin-bottom: 0cm; line-height: normal;\"><b><span lang=\"EN-US\">Possibility to deliver a hard block (GDSII, OpenAccess, Milkyway) for a given design kit.<\/span><\/b><\/p>\n<p class=\"MsoNormal\" style=\"margin-bottom: 0cm; line-height: normal;\"><b><span lang=\"EN-US\"> <\/span><\/b><\/p>\n<p class=\"MsoNormal\" style=\"margin-bottom: 0cm; line-height: normal;\"><b><span lang=\"EN-US\"> <\/span><\/b><\/p>\n<p class=\"MsoNormal\" style=\"margin-bottom: 0cm; line-height: normal;\"><b><span lang=\"EN-US\">Personalized integration into the customers&#8217; project based on specific constraints.<\/span><\/b><\/p>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-0d2f66d elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"0d2f66d\" data-element_type=\"section\" data-settings=\"{&quot;jet_parallax_layout_list&quot;:[]}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-327cab0\" data-id=\"327cab0\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-c6485f5 elementor-widget elementor-widget-image\" data-id=\"c6485f5\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<img decoding=\"async\" src=\"https:\/\/easii-ic.com\/wp-content\/uploads\/elementor\/thumbs\/Capture-decran-2022-11-14-192214-pxpnhua4pd5aucg8lsq7oz0uthifutkjteb8jbt0qo.png\" title=\"Capture d\u2019\u00e9cran 2022-11-14 192214\" alt=\"Capture d\u2019\u00e9cran 2022-11-14 192214\" loading=\"lazy\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-343b5f9 elementor-widget elementor-widget-text-editor\" data-id=\"343b5f9\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"MsoNormal\"><b><br \/>\n  <span lang=\"EN-GB\" style=\"font-family: 'Calibri Light',sans-serif; color: #4472c4; mso-themecolor: accent1; mso-ansi-language: EN-GB;\">Synthesizable Programmable Core (SPC)<\/span><br \/>\n<\/b><span lang=\"EN-GB\" style=\"font-family: 'Arial',sans-serif; color: #4472c4; mso-themecolor: accent1; mso-ansi-language: EN-GB;\"> <\/span><span lang=\"EN-GB\">is a soft FPGA IP for ASICs, SOCs and silicon IPs in general.<\/span><\/p>\n<p class=\"MsoNormal\"><span lang=\"EN-GB\">The great incentive to implement the Synthesizable Programmable Core lies in the reduction of risks associated with errors, specification changes and early adopters&#8217; challenges. The development and verification time for critical blocks can be minimized while bring-up and debugging capabilities are enhanced.<\/span><\/p>\n<p class=\"MsoNormal\"><span lang=\"EN-GB\">In today&#8217;s complex systems, customizable logic can reveal itself as a key element for end user applications: pin swapping, prototype and test chip, different configuration of co-processing, post silicon debug &#8230;<\/span><\/p>\n<p class=\"MsoNormal\"><b><span lang=\"EN-GB\" style=\"font-family: 'Arial',sans-serif; color: #4472c4; mso-themecolor: accent1; mso-ansi-language: EN-GB;\">SPC advantages and benefits<\/span><\/b><\/p>\n<p class=\"MsoNormal\"><b><span lang=\"EN-GB\">RTL design cycle relief<\/span><\/b><\/p>\n<p class=\"MsoNormal\"><span lang=\"EN-GB\">Works as for stand-alone FPGAs: correct or modify a circuit after production and in the field when a system is in service. Reduce time to market by reducing design (verification) time. Reduce risks of bugs, offers to implement workarounds or extra guaranties.<\/span><\/p>\n<p class=\"MsoNormal\" style=\"margin-bottom: 0cm; line-height: normal;\"><span lang=\"EN-GB\"> <\/span><b style=\"color: var( --e-global-color-text ); font-family: var( --e-global-typography-text-font-family ), Sans-serif; font-size: 1rem;\"><span lang=\"EN-GB\">ASIC extended life<\/span><\/b><\/p>\n<ul style=\"margin-top: 0cm;\" type=\"square\">\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">Budget for specifications holes<\/span><\/li>\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">Possibility to upgrade a device at the transistor\/gate level<\/span><\/li>\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">&#8220;Post silicon ASIC design&#8221;<\/span><\/li>\n<\/ul>\n<p class=\"MsoNormal\" style=\"line-height: normal; margin: 0cm 0cm 0cm 36.0pt;\"><span style=\"font-family: 'Arial',sans-serif;\"> <\/span><\/p>\n<p class=\"MsoNormal\"><b><span lang=\"EN-GB\">Focus on the ASIC<\/span><\/b><\/p>\n<ul style=\"margin-top: 0cm;\" type=\"square\">\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">PC is uniquely based on standard ASIC CAD tools and methods:<\/span><\/li>\n<\/ul>\n<p class=\"MsoNormal\" style=\"margin-left: 53.4pt; text-indent: -18.0pt; mso-list: l5 level1 lfo3; tab-stops: list 53.4pt;\"><span lang=\"EN-US\" style=\"font-family: 'Arial',sans-serif; mso-fareast-font-family: Arial; mso-ansi-language: EN-US;\">&#8211;<span style=\"font-variant-numeric: normal; font-variant-east-asian: normal; font-stretch: normal; font-size: 7pt; line-height: normal; font-family: 'Times New Roman';\">       <\/span><\/span><span lang=\"EN-GB\">No constraint for the ASIC design flow<\/span><\/p>\n<p class=\"MsoNormal\" style=\"margin-left: 53.4pt; text-indent: -18.0pt; mso-list: l5 level1 lfo3; tab-stops: list 53.4pt;\"><span lang=\"EN-US\" style=\"font-family: 'Arial',sans-serif; mso-fareast-font-family: Arial; mso-ansi-language: EN-US;\">&#8211;<span style=\"font-variant-numeric: normal; font-variant-east-asian: normal; font-stretch: normal; font-size: 7pt; line-height: normal; font-family: 'Times New Roman';\">       <\/span><\/span><span lang=\"EN-GB\">Accepts the induced limitations (area, circuit type)<\/span><\/p>\n<p class=\"MsoNormal\" style=\"margin-left: 53.4pt; text-indent: -18.0pt; mso-list: l5 level1 lfo3; tab-stops: list 53.4pt;\"><span lang=\"EN-US\" style=\"font-family: 'Arial',sans-serif; mso-fareast-font-family: Arial; mso-ansi-language: EN-US;\">&#8211;<span style=\"font-variant-numeric: normal; font-variant-east-asian: normal; font-stretch: normal; font-size: 7pt; line-height: normal; font-family: 'Times New Roman';\">       <\/span><\/span><span lang=\"EN-GB\">Access to: Simulation, Synthesis, Back end, Test (&#8230;)<\/span><\/p>\n<ul style=\"margin-top: 0cm;\" type=\"square\">\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">Immediate consequences:<\/span><\/li>\n<\/ul>\n<p class=\"MsoNormal\" style=\"margin-left: 53.4pt; text-indent: -18.0pt; mso-list: l1 level1 lfo5; tab-stops: list 53.4pt;\"><span style=\"font-family: 'Arial',sans-serif; mso-fareast-font-family: Arial;\">&#8211;<span style=\"font-variant-numeric: normal; font-variant-east-asian: normal; font-stretch: normal; font-size: 7pt; line-height: normal; font-family: 'Times New Roman';\">       <\/span><\/span><span lang=\"EN-GB\">Transparent models and verification<\/span><\/p>\n<p class=\"MsoNormal\" style=\"margin-left: 53.4pt; text-indent: -18.0pt; mso-list: l1 level1 lfo5; tab-stops: list 53.4pt;\"><span lang=\"EN-US\" style=\"font-family: 'Arial',sans-serif; mso-fareast-font-family: Arial; mso-ansi-language: EN-US;\">&#8211;<span style=\"font-variant-numeric: normal; font-variant-east-asian: normal; font-stretch: normal; font-size: 7pt; line-height: normal; font-family: 'Times New Roman';\">       <\/span><\/span><span lang=\"EN-GB\">Reduction of cost\/delay of the design phase, NRE are reduced<\/span><\/p>\n<p class=\"MsoNormal\" style=\"margin-left: 53.4pt; text-indent: -18.0pt; mso-list: l1 level1 lfo5; tab-stops: list 53.4pt;\"><span lang=\"EN-US\" style=\"font-family: 'Arial',sans-serif; mso-fareast-font-family: Arial; mso-ansi-language: EN-US;\">&#8211;<span style=\"font-variant-numeric: normal; font-variant-east-asian: normal; font-stretch: normal; font-size: 7pt; line-height: normal; font-family: 'Times New Roman';\">       <\/span><\/span><span lang=\"EN-GB\">Flexibility and ease to adapt to special programmable requests<\/span><\/p>\n<p class=\"MsoNormal\" style=\"line-height: normal; margin: 0cm 0cm 0cm 36.0pt;\"><span lang=\"EN-US\"> <\/span><\/p>\n<p class=\"MsoNormal\"><b><span lang=\"EN-GB\">Portability<\/span><\/b><\/p>\n<ul style=\"margin-top: 0cm;\" type=\"square\">\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">RTL IP: no need to silicon-proof every new instance<\/span><\/li>\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">These embedded FPGAs are built with the exact same technology as the ASIC: extensive use of standard cells<\/span><\/li>\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">Full custom design in recent technology nodes comes with high risk and\/or high cost.<\/span><\/li>\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">Synthesizing our IPs out of existing standard cells takes away most of the physical design constraints since the silicon circuits have already been validated.<\/span><\/li>\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">Recent technology nodes,  <\/span><\/li>\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">Standard CAD tools have become very powerful<\/span><\/li>\n<\/ul>\n<p class=\"MsoNormal\" style=\"line-height: normal; margin: 0cm 0cm 0cm 36.0pt;\"><span lang=\"EN-US\"> <\/span><\/p>\n<p class=\"MsoNormal\"><b><span lang=\"EN-GB\">Total flexibility<\/span><\/b><\/p>\n<ul style=\"margin-top: 0cm;\" type=\"square\">\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">Late in the game decision to use an embedded FPGA is made possible due to reduced block delivery delay<\/span><\/li>\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">The scale \/ Size \/ Amount of SPCs are flexible variables<\/span><\/li>\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">The choice is not driven by aspects of the technology or project strategy and architecture<\/span><\/li>\n<li class=\"MsoNormal\"><span lang=\"EN-GB\">Everything happens at the RTL level, every decision remains reversible until Tape-Out<\/span><\/li>\n<\/ul>\n<p class=\"MsoNormal\"><span lang=\"EN-GB\"> <\/span><\/p>\n<p class=\"MsoNormal\" style=\"text-align: right;\" align=\"right\"><a href=\"https:\/\/www.adicsys.com\" rel=\"nofollow noopener\" target=\"_blank\"><span lang=\"EN-GB\" style=\"font-size: 18.0pt; line-height: 107%; font-family: 'Arial',sans-serif; color: gray; mso-themecolor: background1; mso-themeshade: 128; mso-ansi-language: EN-GB;\">www.adicsys.com<\/span><\/a><\/p>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>ADICSYS is an EASii IC subsidiary developing and distributing customizableField Programmable Gate Array technology. ADICSYS stands at the crossroads of ASIC design and FPGA. The company is built on more than ten years of experience in custom FPGA and embedded FPGA, or eFPGA, projects as well as leading edge semiconductor products. ADICSYS designs and licenses [&hellip;]<\/p>\n","protected":false},"author":6,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"elementor_header_footer","meta":{"rank_math_lock_modified_date":false,"footnotes":""},"rankMath":{"parentDomain":"easii-ic.com","noFollowDomains":[],"noFollowExcludeDomains":[],"noFollowExternalLinks":true,"featuredImageNotice":"The featured image should be at least 200 by 200 pixels to be picked up by Facebook and other social media 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