ADICSYS is an EASii IC subsidiary developing
and distributing customizable
Field Programmable Gate Array technology.

ADICSYS stands at the crossroads of ASIC design and FPGA. The company is built on more than ten years of experience in custom FPGA and embedded FPGA, or eFPGA, projects as well as leading edge semiconductor products. ADICSYS designs and licenses soft eFPGA IP (standard cell based) for ASICs and SOCs. These embedded FPGAs are technology independent and fully integrated into standard RTL design flows

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Key features

  • Synthesizable IP
  • Fully integrated into standard flows
  • RTL to FPGA bitstream
  • Technology independent
  • Highly scalable and customizable
  • Bist for manufacturing test

Domain specific FPGA

  • FPGA core based on proven eFPGA
  • RTL to bitstream compilation flow

▪ Independent and distributable

▪ Embeddable in final application

  • Specialized Team: 20 years of FPGA core design and integration
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Programmable IPs in our catalog:

§ Immediate access – Download efpga IP datasheet

Customized programmable IPs:

§ Dimensions and aspect ratio

§ Architecture parameters (LUT count and style, routing density…)

§ Customization for special constraints (area, performance, power)

§ Customization for special design types or use case

Verilog programmable IP comprising:

§ Synthesizable RTL – Constraint files

§ ADICSYS compilation software: Acompile

§ Bitstream loader & Test program (BIST)

Possibility to deliver a hard block (GDSII, OpenAccess, Milkyway) for a given design kit.

Personalized integration into the customers’ project based on specific constraints.

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Synthesizable Programmable Core (SPC)
is a soft FPGA IP for ASICs, SOCs and silicon IPs in general.

The great incentive to implement the Synthesizable Programmable Core lies in the reduction of risks associated with errors, specification changes and early adopters’ challenges. The development and verification time for critical blocks can be minimized while bring-up and debugging capabilities are enhanced.

In today’s complex systems, customizable logic can reveal itself as a key element for end user applications: pin swapping, prototype and test chip, different configuration of co-processing, post silicon debug …

SPC advantages and benefits

RTL design cycle relief

Works as for stand-alone FPGAs: correct or modify a circuit after production and in the field when a system is in service. Reduce time to market by reducing design (verification) time. Reduce risks of bugs, offers to implement workarounds or extra guaranties.

ASIC extended life

  • Budget for specifications holes
  • Possibility to upgrade a device at the transistor/gate level
  • “Post silicon ASIC design”

Focus on the ASIC

  • PC is uniquely based on standard ASIC CAD tools and methods:

No constraint for the ASIC design flow

Accepts the induced limitations (area, circuit type)

Access to: Simulation, Synthesis, Back end, Test (…)

  • Immediate consequences:

Transparent models and verification

Reduction of cost/delay of the design phase, NRE are reduced

Flexibility and ease to adapt to special programmable requests


  • RTL IP: no need to silicon-proof every new instance
  • These embedded FPGAs are built with the exact same technology as the ASIC: extensive use of standard cells
  • Full custom design in recent technology nodes comes with high risk and/or high cost.
  • Synthesizing our IPs out of existing standard cells takes away most of the physical design constraints since the silicon circuits have already been validated.
  • Recent technology nodes,
  • Standard CAD tools have become very powerful

Total flexibility

  • Late in the game decision to use an embedded FPGA is made possible due to reduced block delivery delay
  • The scale / Size / Amount of SPCs are flexible variables
  • The choice is not driven by aspects of the technology or project strategy and architecture
  • Everything happens at the RTL level, every decision remains reversible until Tape-Out